Nalesh, S: search on Z-Library

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1

[IEEE 2013 25th International Conference on Microelectronics (ICM) - Beirut, Lebanon (2013.12.15-2013.12.18)] 2013 25th International Conference on Microelectronics (ICM) - Design of a low power 64 point FFT architecture for WLAN applications

Kala, S, Nalesh, S, Nandy, S K, Narayan, Ranjani

Year:

2013

Language:

english

File:

PDF, 986 KB

english, 2013

2

[IEEE 2013 IEEE International Symposium on Circuits and Systems (ISCAS) - Beijing (2013.5.19-2013.5.23)] 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) - High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit

Kala, S., Nalesh, S., Maity, Arka, Nandy, S. K., Narayan, Ranjani

Year:

2013

Language:

english

File:

PDF, 613 KB

english, 2013

3

[IEEE 2015 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) - Indore, India (2015.12.21-2015.12.23)] 2015 IEEE International Symposium on Nanoelectronic and Information Systems - Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array

Nalesh, S., Madhu, Kavitha T., Das, Saptarsi, Nandy, S.K., Narayan, Ranjani

Year:

2015

Language:

english

File:

PDF, 274 KB

english, 2015

4

[IEEE 2014 Fifth International Symposium on Electronic System Design (ISED) - Surathkal, Mangalore, India (2014.12.15-2014.12.17)] 2014 Fifth International Symposium on Electronic System Design - Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems

Kala, S., Nalesh, S., Nandy, S.K., Narayan, Ranjani

Year:

2014

Language:

english

File:

PDF, 559 KB

english, 2014

5

A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths

Das, Saptarsi, Madhu, Kavitha, Krishna, Madhav, Sivanandan, Nalesh, Merchant, Farhad, Natarajan, Santhi, Biswas, Ipsita, Pulli, Adithya, Nandy, S.K., Narayan, Ranjani

Journal:

Journal of Systems Architecture

Year:

2014

Language:

english

File:

PDF, 1.94 MB

english, 2014

6

[IEEE 2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC), 2015 IEEE 7th International Symposium on Cyberspace Safety and Security (CSS) and 2015 IEEE 12th International Conf on Embedded Software and Systems (ICESS) - New York, NY, USA (2015.8.24-2015.8.26)] 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems - Compiling HPC Kernels for the REDEFINE CGRA

Madhu, Kavitha T., Das, Saptarsi, S., Nalesh, Nandy, S. K., Narayan, Ranjani

Year:

2015

Language:

english

File:

PDF, 445 KB

english, 2015

7

[IEEE 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) - Kolkata, India (2016.1.4-2016.1.8)] 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) - RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels

Das, Saptarsi, Sivanandan, Nalesh, Madhu, Kavitha T., Nandy, Soumitra K., Narayan, Ranjani

Year:

2016

Language:

english

File:

PDF, 169 KB

english, 2016

8

[IEEE 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV) - Agios Konstantinos, Samos, Greece (2014.7.14-2014.7.17)] 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV) - Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath

Madhu, Kavitha T, Das, Saptarsi, C, Madhava Krishna, S, Nalesh, Nandy, S. K., Narayan, Ranjani

Year:

2014

Language:

english

File:

PDF, 1.93 MB

english, 2014

9

[IEEE 2015 28th International Conference on VLSI Design (VLSID) - Bangalore, India (2015.1.3-2015.1.7)] 2015 28th International Conference on VLSI Design - Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations

Merchant, Farhad, Maity, Arka, Mahadurkar, Mahesh, Vatwani, Kapil, Munje, Ishan, Krishna, Madhava, Nalesh, S., Gopalan, Nandhini, Raha, Soumyendu, Nandy, S.K., Narayan, Ranjani

Year:

2015

Language:

english

File:

PDF, 531 KB

english, 2015

10

Energy aware synthesis of application kernels through composition of data-paths on a CGRA

S., Nalesh, Madhu, Kavitha T., Das, Saptarsi, Nandy, S.K., Narayan, Ranjani

Journal:

Integration, the VLSI Journal

Year:

2017

Language:

english

File:

PDF, 1.30 MB

english, 2017

11

[IEEE 2018 8th International Symposium on Embedded Computing and System Design (ISED) - Cochin, India (2018.12.13-2018.12.15)] 2018 8th International Symposium on Embedded Computing and System Design (ISED) - Design Space Exploration of Convolution Algorithms to Accelerate CNNs on FPGA

S, Kala, Paul, Debdeep, Jose, Babita R, S, Nalesh

Year:

2018

File:

PDF, 360 KB

2018

12

[IEEE 2019 32nd IEEE International System-on-Chip Conference (SOCC) - Singapore (2019.9.3-2019.9.6)] 2019 32nd IEEE International System-on-Chip Conference (SOCC) - Efficient Hardware Acceleration of Convolutional Neural Networks

S., Kala, Jose, Babita R, Mathew, Jimson, S, Nalesh

Year:

2019

File:

PDF, 333 KB

2019

13

[IEEE 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) - Delhi, NCR, India (2019.1.5-2019.1.9)] 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) - UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs

S, Kala, Mathew, Jimson, Jose, Babita R, S, Nalesh

Year:

2019

Language:

english

File:

PDF, 1.19 MB

english, 2019

14

[IEEE 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) - Taormina, Italy (2018.4.9-2018.4.12)] 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) - Two dimensional FFT architecture based on radix-4 3 algorithm with efficient output reordering

Kala, S, Nalesh, S, Jose, Babita R, Mathew, Jimson, Ottavi, Marco

Year:

2018

Language:

english

File:

PDF, 298 KB

english, 2018

15

A Hardware Architecture for Radial Basis Function Neural Network Classifier

Mohammadi, Mahnaz, Krishna, Akhil, S, Nalesh, Nandy, S. K.

Journal:

IEEE Transactions on Parallel and Distributed Systems

Year:

2018

Language:

english

File:

PDF, 1.45 MB

english, 2018

16

Radix-43 based two-dimensional FFT architecture with efficient data reordering scheme

S., Kala, Mathew, Jimson, Jose, Babita R., S., Nalesh

Journal:

IET Computers & Digital Techniques

Year:

2019

Language:

english

File:

PDF, 3.20 MB

english, 2019

17

[IEEE 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) - Delhi, NCR, India (2019.1.5-2019.1.9)] 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) - UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs

S, Kala, Mathew, Jimson, Jose, Babita R, S, Nalesh

Year:

2019

File:

PDF, 1.19 MB

2019

18

Efficient CNN Accelerator on FPGA

Kala, S, Nalesh, S

Journal:

IETE Journal of Research

Year:

2020

File:

PDF, 823 KB

2020

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